The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device that selects one of a plurality of output enable signals in synchronization with an output signal of a delay locked loop (DLL).
Synchronous memory devices, e.g., double data rate (DDR) synchronous dynamic random access memory (SDRAM), are designed to generate a plurality of output enable signals in synchronization with a DLL clock (CLK_DLL) and having different pulse widths depending on a burst length, and to selectively use one of them according to a column address strobe (CAS) latency.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 1, a DLL 10 delays an external clock CLK_EXT to generate a DLL clock CLK_DLL. An output enable signal generator 12 generates a plurality of output enable signals OE0, OE1, OE1.5, . . . , OEN in response to the DLL clock CLK_DLL and outputs one of the output enable signals OE0, OE1, OE1.5, . . . , OEN as a final output enable signal according to a CAS latency CL. The final output enable signal masks a portion of the DLL clock CLK_DLL used for data output.
FIG. 2 is a block diagram of the DLL 10 shown in FIG. 1.
Referring to FIG. 2, the DLL 10 includes a buffer 20, a phase comparator 21, a delay controller 22, variable delay line 23, a duty corrector 24 and a delay model 25.
The buffer 20 buffers the external clock CLK_EXT to generate a source clock CLK_SRC. The phase comparator 21 compares a phase of the source clock CLK_SRC with a phase of a feedback clock CLK_FDB. The delay controller 22 generates a delay control signal CTR_DL in response to an output signal of the phase comparator 21. The variable delay line 23 delays the source clock CLK_SRC in response to the delay control signal CTR_DL. The duty corrector 24 corrects a duty of the delayed source clock CLK_SRC and outputs the corrected source clock as the DLL clock CLK_DLL. The delay model 25 outputs the feedback clock CLK_FDB by reflecting a delay of a real clock/data path.
Since the configuration and operation of the DLL 10 is well known, their detailed description will be omitted for conciseness.
FIG. 3 is a timing diagram of the DLL clock CLK_DLL and the plurality of output enable signals in the conventional semiconductor memory device of FIG. 1. It is assumed herein that it takes 15 ns to output internal data after a read command RD according to specification. Therefore, when “tCK” of the external clock CLK_EXT is 2.5 ns, the CAS latency is 6. In addition, it is assumed herein that a delay time T2 of the delay model 25 is 2 ns and a delay time T1 of the variable delay line 23 is 0.5 ns in a delay locked state. For convenience, delay time of the buffer 20 and the duty corrector 24 is not considered.
Referring to FIG. 3, the DLL 10 performs a DLL operation to generate the DLL clock CLK_DLL. Then, the read command RD is applied and the DLL clock CLK_DLL leads the external clock CLK_EXT. That is, the DLL clock CLK_DLL is generated after the external clock CLK_EXT is delayed by the delay time T1 of the variable delay line 23. The first DLL clock 0D corresponds to the first external clock 0E.
Since the CAS latency is 6, data must be outputted in synchronization with the sixth external clock 5E. Therefore, after the sixth DLL clock 5E is delayed by “T2”, the data is outputted in synchronization with the DLL clock CLK_DLL. Consequently, the first data DTO is outputted in synchronization with the sixth external clock 5E and the next data DT1, DT2 and DT3 are outputted in synchronization with the external clock CLK_EXT.
After the read command RD is applied, an internal read pulse signal IRDP is activated and an output enable signal “OE0” is generated in response to the internal read pulse signal IRDP. The output enable signal “OE0” has a pulse width corresponding to a burst length. Using the output enable signal “OE0”, output enable signals “OE1” to “OEN” are generated in response to the DLL clock CLK_DLL. In other words, the output enable signals “OE1” to “OEN” are generated by shifting the output enable signal “OE0”. More specifically, the output enable signals “OE1” to “OEN” are signals that are alternately generated at rising edges and falling edges. For convenience, only several output enable signals are shown in FIG. 3.
For example, when an output enable signal “OE4.5” is used for masking the sixth DLL clock 5D, the output enable signal generator 12 of FIG. 1 outputs the output enable signal “OE4.5” using the CAS latency signal CL having the CAS latency of 6.
However, in order to perform such an operation, the output enable signal to be used according to “tCK” and the CAS latency must be set. In other words, a total delay time of the DLL 10 in the delay locked state is defined as “the delay time (T1) of the variable delay line 23+the delay time (T2) of the delay model 25” and is 2.5 ns. Therefore, when a designer must predict the total delay time through a simulation and set “OE4.5” as the final output enable signal to be used when the CAS latency is 6. For example, when the total delay time is 5 ns, the designer must set “OE3” as the final output enable signal even though the CAS latency is 6.
As described above, since the total delay time of the DLL 10 in the delay locked state changes, the designer must previously predict the total delay time and set the output enable signal suitable for “tCK” and the CAS latency through a simulation verification.